The present invention relates to a semiconductor device and manufacture process, and more especially, to a structure and method for inter-metal dielectric layer using low dielectric constant organic dielectric material and low dielectric constant inorganic dielectric material.
In the electric and semiconductor industry, dielectric materials are widely applied to the isolations for devices and conductive layers. One important application of the dielectric materials is the inter-metal dielectric layer among the multilevel-interconnect.
The inter-metal dielectric layer is formed among the multilevel-interconnect to provide electrical insulation. As the integrated circuit technology trends toward increase of the device density and decrease of the device size, the density of interconnects increases and the allowed areas for the insulation regions must be reduced. However, there are always parasitic capacitors existent between adjacent interconnect lines and between the adjacent interconnect layers. Typically, for a standard capacitor, the capacitance C=k∈oA/d, wherein A is the surface area of the conductive line, ∈o is the permittivity of vacuum, d and k are respectively the thickness and permittivity of the dielectric material employed. When the thickness d of the employed dielectric layer decreases, the capacitance C will increase, and the RC time delay will therefore increase. Because the signal transmitting time is proportional to the RC time delay, the increase of the capacitance will be harmful to device characteristics such as frequency response.
For the reason to lower the capacitance and to reduce the influence about parasitic capacitor to the integrated circuits, seeking substitutional materials to reduce the permittivity, that is, dielectric constant of the inter-metal dielectric layer, would be an appropriate way without change the circuit layout. Typical silicon oxide materials, such as silicon dioxide, boro silicate glass, (BSG), phospho silicate glass (PSG), boro-phospho silicate glass (BPSG), or tetra-ethyl-ortho-silicate-oxide (TEOS-oxide), are not ideal inter-metal dielectric layers for their high dielectric constants within the range of about 3.9 to 4.5. An appropriate substitutional material is the organic dielectric material, which has dielectric constant around 2.5. With such a low dielectric constant, the parasitic capacitance and the RC time delay can be substantially lowered.
Due to the spin-on coating method that are usually employed for the fabrication of the organic dielectric material, moisture is always found during the fabrication. Therefore, organic dielectric material can not be formed directly in contact with metal. There must be a liner oxide, which is typically a tetra-ethyl-ortho-silicate-oxide (TEOS-oxide) layer, formed between organic dielectric material and metal. In FIG. 1, a cross-sectional view illustrating a traditional structure of a semiconductor wafer with an inter-metal dielectric layer formed of organic dielectric material is shown. On semiconductor substrate 10 with metal line 12, liner oxide 14, organic dielectric layer 16, and cap layer 18 formed sequentially, a contact hole 20 is opened through the cap layer 18, the organic dielectric layer 16, and the liner oxide 14 to expose a portion of the metal line 12.
Although the parasitic capacitance can be reduced with above dielectric structure, another problem about thermal conductivity arises. Due to the poor thermal conductivity of the organic dielectric material, the heat generated by the metal line is hard to be diffused and transferred through the organic dielectric material, and therefore the reliability of the metal line is decreased. Furthermore, because the contact hole 20 passes through the organic dielectric layer 16, the released moisture will react upon the metal material deposited subsequently, and damage the electrical conductivity of the contact hole.
FIG. 2 depicts an improved structure of inter-metal dielectric layer, wherein the isolation within a conductive layer is formed of organic dielectric layer 16 and the isolation between different conductive layers is formed of cap layer 18. Typically, the isolation thickness between different conductive layers is much greater than that within a conductive layer. At the isolation region between different conductive layers, the parasitic capacitance is smaller, but the thermal conductivity has a greater influence. Therefore, in consideration of both parasitic capacitance and thermal conductivity, the structure shown in FIG. 2 can lower the parasitic capacitance within a conductive layer and improve the thermal conductivity of inter-metal dielectric layer.
However, in the structure shown in FIG. 2, the liner oxide 14 must serve as a stopping layer when the: organic dielectric layer 16 is etched back, in addition to serve as a isolation layer between the metal line 12 and the organic dielectric layer 16. To be the stopping layer, the liner oxide 14 must be formed with a considerable thickness to prevent from over etching and damage of the underlying metal line 12. Typically, the thickness employed for this liner oxide 14 is ranged of about 1000 to 1500 angstroms. The thick liner oxide will increase the parasitic capacitance within a conductive layer. As the semiconductor manufacture tends to increase density of device, the area allowed for the dielectric layer within a conductive layer is decreased day by day. The effect that the parasitic capacitance increased by the thick liner oxide will become more and more important.
The present invention proposes a novel structure and method for inter-metal dielectric layer using low dielectric constant organic material and low dielectric constant inorganic material. The parasitic capacitance can be decreased as the thermal conductivity is substantially kept. The present invention is to fabricate an inter-metal dielectric layer with low dielectric constant organic material providing isolation within a conductive layer and with low dielectric constant inorganic material providing isolation between different conductive layers.
Firstly, a conductive layer and an anti-reflection coating layer are formed in sequence on a semiconductor substrate. A photolithography and an anisotropic etching process are then carried out to pattern the conductive layer and the anti-reflection coating layer. An interconnecting structure with anti-reflection coating is thus formed. A dielectric liner is deposited on the substrate and then etched back. Dielectric spacers are thus formed on the sidewalls of the conductive layer and the anti-reflection coating layer.
Thereafter, an organic dielectric layer is coated on the semiconductor substrate and then etched back with the anti-reflection coating layer as stopping layer. The anti-reflection coating layer is then removed. An inorganic dielectric layer and a dielectric cap layer are deposited in sequence on the conductive layer, the dielectric spacers and the organic dielectric layer. A chemical mechanical polishing is carried out to planarize the dielectric cap layer. Finally, the inorganic dielectric layer and the dielectric cap layer are etched to form contact holes.
By implementing above processes, a structure of a conductive line with an inter-metal dielectric layer is fabricated. The structure comprises a conductive line formed on a semiconductor substrate; dielectric spacers formed on the sidewalls of the conductive line; an organic dielectric layer formed on the substrate and filling the regions among the conductive line; an inorganic dielectric layer formed on the conductive line, the dielectric spacers, and the organic dielectric layer; a planarized cap layer formed on the inorganic dielectric layer.